Conventional liquid crystal display devices display images through changes in light transmittance caused by the behavior of liquid crystals having dielectric anisotropy in an applied electric field. For this purpose, the liquid crystal display device is provided with a liquid crystal display panel, in which pixel regions are arranged in a matrix form, and a drive circuit to drive the liquid crystal display panel.
The liquid crystal display panel comprises first and second substrates joined to each other with a predetermined space therebetween, and a liquid crystal layer disposed between the first and second substrates. To drive the liquid crystal layer for each pixel, the first substrate includes a plurality of gate lines and a plurality of data lines orthogonally crossing each other to define the pixel regions. Each pixel region has a pixel electrode formed therein, and a thin film transistor formed near to the crossing of each gate line and data line. The thin film transistor turns on in response to scanning signals from the gate line and applies data signals from the data line to the pixel electrode.
The second substrate includes a black matrix layer to shield light at a portion that does not include the pixel regions, and color filter layers formed in the respective pixel regions to generate colors. The second substrate may also include a common electrode opposite to the pixel electrodes to generate electric fields to drive the liquid crystal layer.
The drive circuit comprises a gate driver to drive the gate lines, a data driver to drive the data lines, and a timing controller to supply control signals and data signals to control the gate driver and data driver.
The gate driver is provided with a shift register to sequentially output scan pulses to the respective gate lines. The shift register is composed of a plurality of stages dependently connected with each other. The plural stages serve to sequentially output the scan pulses and then sequentially scan the gate lines of the liquid crystal panel.
Specifically, a first stage among the plural stages receives a start signal from the timing controller as a trigger signal, and the remaining stages receive output signals from their prior stages as the trigger signal. In addition, each of the plural stages is applied with at least one of plural clock pulses having sequential phase differences. Accordingly, the scan pulses can be sequentially outputted from the first stage to the last stage.
In such a conventional gate driver, a separate gate driver integrated circuit (IC) having the shift register of the gate driver embedded therein is formed and connected to a gate line pad of the liquid crystal display panel through a mounting process and the like.
FIG. 1 is a partially exploded perspective view of a conventional liquid crystal display device.
Referring to FIG. 1, the conventional liquid crystal display device comprises first and second substrates 1 and 2 bonded to each other with a predetermined space therebetween, and a liquid crystal layer 3 formed between the first and second substrates 1 and 2.
More specifically, the first substrate 1 has a plurality of gate lines 4 arranged at constant intervals in one direction, and a plurality of data lines 5 arranged at constant intervals in another direction perpendicular to the gate lines to define pixel regions P therebetween. Each of the pixel regions P defined by the gate lines 4 and data lines 5 includes a pixel electrode 6 and a thin film transistor T disposed near a crossing point of the gate line 4 and the data line 5. The thin film transistor T is turned on or off in response to a scanning signal from the gate line 4 and applies a data signal from the data line 5 to the pixel electrode 6. This substrate is called a thin film transistor array substrate.
The second substrate 2 is provided with a black matrix layer 7 to shield light from passing through a portion excluding the pixel regions P. The second substrate 2 also includes RGB color filter layers 8 to exhibit colors and a common electrode 9 to realize an image. This substrate is called a color filter array substrate.
Generally, a method for manufacturing a liquid crystal display device can be divided into a cell array process, an assembly process, and a module process.
The cell array process includes a thin film transistor array process and a color filter array process. The thin film transistor array process includes steps of defining a plurality of first panel regions on a first mother substrate, and forming a thin film transistor array including gate lines, data lines, thin film transistors and pixel electrodes in the respective panel regions. The color filter array process includes steps of defining a plurality of second panel regions on a second mother substrate, and forming a color filter array comprising a black matrix layer, RGB color filter layers and a common electrode in the respective second panel regions.
The assembly process includes steps of forming a sealant at an edge of each panel region of the first or second mother substrate, depositing liquid crystals in each panel region of the first or second mother substrate, and aligning and bonding the first and second mother substrates to each other. Additionally, the assembly process comprises cutting the bonded first and second mother substrates into unit panel regions, and inspecting the respective unit panel regions by auto-probe inspection.
The module process is a process to attach a drive IC to each of the unit panels, followed by assembling a backlight unit thereto.
When the cell array process is completed, defects due to opens or shorts of the respective signal lines of the thin film transistor array are checked (that is, a mass product system inspection, which will be hereinafter referred to as an “MPS inspection,” is carried out) before the assembly process, to determine if the product is defective, and a repair process is additionally performed if it is determined that a certain product has a defect.
For the MPS inspection, MPS wires for the inspection are formed during the cell array process and then removed by the cutting process.
FIG. 2 is a plan view illustrating the MPS wires of the conventional liquid crystal display device.
Plural panel regions are defined on a mother substrate 20. Here, each of the panel regions has a display area 21 and a non-display area 22 defined therein. In FIG. 2, two panel regions are shown.
The display area of each panel region on the mother substrate 20 is formed with the thin film transistor array (not shown) as shown in FIG. 1, and the non-display area of each panel region is formed with MPS wires 23 and MPS pads 24.
The MPS wires 23 typically comprise about 5 to 6 wires, such as a wire “G/E” for inspecting gate lines of even order, a wire “G/O” for inspecting gate lines of odd order, a wire “D/E” for inspecting data lines of even order, a wire “D/O” for inspecting data lines of odd order, a wire “Vcom” for inspecting a common line, a wire “GND” for inspecting a ground line, a wire “VDD” for inspecting a voltage line, etc. The MPS wires 23 are formed on a gate pad region or a data pad region of the non-display area.
In addition, the MPS wires 23 and MPS pads 24 are formed simultaneously when forming the gate lines of the thin film transistor array. The MPS wires 23 are connected to corresponding gate, data, common, ground, voltage, and signal lines via the same material as that used for the pixel electrodes.
Recently, however, a gate-in-panel (GIP) technique is used, in which a shift register is directly formed on the liquid crystal display panel without forming a separate gate driver IC, to reduce material costs, the number of processes, and a process time. In other words, the shift register of the gate driver is formed in the liquid crystal display panel.
There will be described hereinafter a conventional GIP type liquid crystal display device.
FIG. 3 is a plan view of the conventional GIP type liquid crystal display device.
Referring to FIG. 3, for the GIP type liquid crystal display device, a lower substrate 31 is bonded to an upper substrate 32 via a sealant 40 with a predetermined space therebetween. Here, the lower substrate 31 has a larger size than that of the upper substrate 32 to form a non-display area on which a data driver and the like are mounted, and display areas within the region generally bounded by the sealant 40 on the bonded upper and lower substrates 31 and 32. In FIG. 3, the non-display area of the lower substrate 31 is mounted with a tape carrier package (TCP) 37.
In addition, each display area of the bonded upper and lower substrates 31 and 32 is divided into an active area (A/A) and a dummy area (D).
As described above, although not shown in the drawings, the active area (A/A) in the display area of the lower substrate 31 includes the gate lines, data lines, pixel electrodes, and the thin film transistors, and the active area (A/A) in the display area of the upper substrate 32 is formed with the black matrix layer, color filter layers and the common electrode (see FIG. 1).
The dummy area (D) in the display area of the lower substrate 31 is formed with a common line (not shown in the drawings), a GIP gate driver 33, a GIP dummy gate driver 34, and signal lines 35 to apply various signals (clock signal, enable signal, start signal, common voltage, etc.) output from the timing controller to the GIP gate driver 33 and GIP dummy gate driver 34, and the dummy area D in the display area of the upper substrate 32 is formed with the black matrix layer.
When the signal lines 35 are exposed to an electrostatic discharge during processing, elements of the thin film transistor array may be damaged. Thus, in order to prevent this phenomenon, electrostatic discharge prevention circuits are provided to the signal lines 35, and the signal lines 35 are connected to a first TCP 37.
A liquid crystal layer is formed between the upper and lower substrates 31 and 32 in the display area.
In such a GIP type liquid crystal display panel constructed as above, it is necessary to form the MPS wires as described in FIG. 2.
However, compared with a typical liquid crystal display device (see FIG. 2), the GIP type liquid crystal display device further comprises not only the GIP gate driver 33 and GIP dummy gate driver 34 but also the signal lines 35 to apply the signals thereto formed in the dummy area as described above. Furthermore, compared with the typical liquid crystal display device having 5 to 6 MPS wires, the GIP type liquid crystal display device requires more MPS wires (about 10 to 15 MPS wires) since it is necessary to check for opens or shorts of the signal lines.
Thus, the GIP type liquid crystal display device has shortcomings in that it is difficult to obtain sufficient space to form the MPS wires and to check for defects in the respective lines.
In addition, since the MPS wires are preferably concentrated on the first TCP region for the GIP type liquid crystal display device to check for defective signal lines, it is further difficult to secure the space for the MPS wires.